//module  dds_AM                        //K=300
//(
//input clkfc,rst_n,
//input AM_date_k,
//input [3:0]step,
//output [17:0]date_AM_final
//);
////reg [19:0]date_k=20'd60000;
//reg [19:0]add_sin;
//always@(posedge clkfc,negedge rst_n)
//begin
// if(!rst_n)
//  add_sin<=20'd0;
// else
//  begin
//  add_sin<=add_sin+AM_date_k;
//  end
//end
//assign add_sin_12=add_sin[19:8];
//wire [11:0]add_sin_12;
//wire [13:0]date_sin;
//sinrom_add12_date14	sinrom_add12_date14_inst (
//.address ( add_sin_12 ),
//.clock ( clkfc ),
//.q ( date_sin )
//);
//sin1khz sin1khz_inst
//(
//	.rst_n(rst_n) ,	// input  rst_n_sig
//	.clkfc(clkfc) ,	// input  clkfc_sig
//	.add_sin_1k(add_sin_1k) ,	// output [19:0] add_sin_1k_sig
//	.date_sin_1k(date_sin_1k) 	// output [13:0] date_sin_1k_sig
//);
//wire[13:0]date_sin_1k;
//reg signed [13:0]date_sin_signed;
//reg signed [13:0]date_sin_1k_signed;
//always@(posedge clkfc,negedge rst_n )
//begin
// if(!rst_n)  begin
//  date_sin_signed<=14'd0;
//  date_sin_1k_signed<=14'd0;
//  end
// else        begin
//   date_sin_signed<=date_sin-14'd8192;
//   date_sin_1k_signed<=date_sin_1k-14'd8192;
// 
// end
//end
//reg[14:0]date_AM;
//wire signed [27:0] date_AM_signed;
//mult	mult_inst (
//	.dataa ( date_sin_signed ),
//	.datab ( date_sin_1k_signed ),
//	.result ( date_AM_signed )
//	);
//wire signed [13:0]date_AM_signed_fact;
//assign  date_AM_signed_fact=date_AM_signed[26:13];
//always @(posedge clkfc,negedge rst_n)  begin
// if(!rst_n)
//  date_AM<=15'd0;
// else       begin
//   date_AM<=date_AM_signed_fact+15'sd8192;    //date_AM最高位是符号位，只需要引出低十四位 ，，，这里的位数应该用影响，做出修改把15位改成了14位
//  end
//end
//wire  [13:0]date_AM_divide;             //只要去低十四位就好了
//divide_device	divide_device_inst (
//	.denom ( 14'd10 ),
//	.numer ( date_AM[13:0] ),
//	.quotient ( date_AM_divide ),
//	.remain ( remain_sig )
//	);
//
//step_mult	step_mult_inst (
//	.dataa ( date_AM_divide ),
//	.datab ( step ),
//	.result ( date_AM_final )
//	);
//
//endmodule 



module  dds_AM                        //K=300
(
input clkfc,rst_n,
input [31:0]AM_date_k,
input [13:0]k,       //k=100-modulation
input [13:0]b,                //b=modulation  换算成 16383*modulation/100
output [13:0]date_AM_final
);

//reg [31:0] AM_date_k=32'd42949673;
assign date_AM_final=date_AM[13:0];
reg [31:0]add_sin;
always@(posedge clkfc,negedge rst_n)
begin
 if(!rst_n)
  add_sin<=32'd0;
 else
  begin
  add_sin<=add_sin+AM_date_k;
  end
end
assign add_sin_12=add_sin[31:20];
wire [11:0]add_sin_12;
wire [13:0]date_sin;
sinrom_add12_date14	sinrom_add12_date14_inst (
.address ( add_sin_12 ),
.clock ( clkfc ),
.q ( date_sin )
);
wire [13:0]date_sin_1k;
sin1khz sin1khz_inst
(
	.rst_n(rst_n) ,	// input  rst_n_sig
	.clkfc(clkfc) ,	// input  clkfc_sig
//	.add_sin_1k(add_sin_1k) ,	// output [19:0] add_sin_1k_sig
	.date_sin_1k(date_sin_1k) 	// output [13:0] date_sin_1k_sig
);
wire[13:0]date_sin_1k_result;
multy	multy_inst (
	.dataa ( date_sin_1k_result ),
	.datab ( k ),
	.result ( date_sin_1k_result_multy )
	);
wire[13:0]date_sin_1k_result_multy;
divide_device	divide_device_inst (
	.denom ( 14'd100 ),
	.numer ( date_sin_1k ),
	.quotient ( date_sin_1k_result ),
	.remain ( remain_sig )
	);
wire [13:0]date_1;
assign date_1=date_sin_1k_result_multy+b;
wire signed [14:0]date_1_signed;
assign date_1_signed[13:0]=date_1;
assign date_1_signed[14]=1'b0;
//wire[13:0]date_sin_1k;
reg signed [13:0]date_sin_signed;
reg signed [13:0]date_sin_1k_signed;
always@(posedge clkfc,negedge rst_n )
begin
 if(!rst_n)  begin
  date_sin_signed<=14'd0;
 // date_sin_1k_signed<=14'd0;
  end
 else        begin
   date_sin_signed<=date_sin-14'd8192;
  // date_sin_1k_signed<=date_sin_1k-14'd8192;
 
 end
end

wire signed [28:0] date_AM_signed;
mult_date_k	mult_date_k_inst (
	.dataa ( date_1_signed ),
	.datab ( date_sin_signed ),
	.result ( date_AM_signed )
	);
reg signed [14:0]date_AM;
wire signed [13:0]date_AM_signed_fact;
assign  date_AM_signed_fact=date_AM_signed[27:14];
always @(posedge clkfc,negedge rst_n)  begin
 if(!rst_n)
  date_AM<=15'd0;
 else       begin
   date_AM<=date_AM_signed_fact+15'sd8192;    //date_AM最高位是符号位，只需要引出低十四位 ，，，这里的位数应该用影响，做出修改把15位改成了14位
  end
end


endmodule 